1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory element utilizing a trench capacitor and, more particularly, to a method of easily forming a trench capacitor.
2. Related Background Art
The packing density of dynamic random access memories (DRAMs) and metal oxide semiconductor (MOS) memories has been increased year by year, and the age of 1-Mbit or 1-Gbit memories from 64- to 256-kbit memories is coming.
A conventional capacitive memory cell consists of a capacitor for storing signal charge and a MOS transistor for reading out the signal charge. In order to achieve a higher packing density, the capacitor occupying most of the cell area must be made compact because micropatterning of the MOS transistor poses limitations.
Various techniques have been proposed to reduce the size of the capacitor in the memory cell. If the size of the capacitor is simply reduced on a two-dimensional plane, the amount of signal charge is reduced. In order to compensate for this, the thickness of an insulating layer between the electrodes must be reduced or a material having a higher dielectric constant than that of SiO.sub.2 must be used. A trench capacitor type memory cell is proposed to reduce the planar area of the capacitor without using the special material described above.
FIG. 1 is a schematic sectional view showing the basic structure of a conventional trench capacitor type memory cell.
Referring to FIG. 1, the memory cell consists of a trench capacitor for storing signal charge and a MOS transistor for reading out the signal charge from the trench capacitor. The trench capacitor is formed as follows:
A deep groove or trench 2 is formed in a silicon substrate 1 by reactive ion etching (RIE) or the like. An oxide film 3 is formed on the inner wall surface of the trench 2. Polysilicon is deposited to cover the entire surface including the trench 2. The polysilicon film is etched back until the surface of the substrate 1 is exposed. In this state, polysilicon 4 is left in only the trench 2. The substrate 1 opposes the polysilicon 4 through the oxide film 3, thereby constituting a trench capacitor.
It is difficult to detect an etching end timing in the etch-back process of polysilicon deposited on the substrate surface excluding the trench 2. Therefore, the fabrication process cannot be simplified or cannot be made easy.